1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing same, and more particularly, to a semiconductor memory device wherein a head portion of a semiconductor pillar having a conductive side wall is brought into contact with a conductive pattern, and a method of manufacturing same.
2. Description of the Related Art
FIGS. 1 and 2, respectively, show cross-sectional views of a pillar-shaped DRAM (Dynamic Random Access Memory) and a ROM (Read Only Memory) of the prior art.
In FIG. 1 a SiO.sub.2 film 2 is formed on a silicon substrate 1, and a semiconductor pillar 3 is formed on the SiO.sub.2 film 2 and consists of a first conductive layer (storage electrode) 4, p.sup.- type Si layer 5, channel doped layer 6, and a second conductive layer (drain) 7. The DRAM of FIG. 1 further comprises a dielectric film 8, a gate insulating film (SiO.sub.2) 9 a second conductive layer (electrode) 10, a polysilicon word line (gate) 11, an interlaminar insulating film 12 such as a PSG film, etc., and an aluminum bit line 13.
Further, as shown in FIG. 2, the ROM likewise comprises a pillar 3 formed on a silicon substrate 1 having a n.sup.+ drain region 7, dielectric film 2, a gate insulating film 9, a doped polysilicon gate electrode (word line) 11, a PSG interlaminar insulting film 12, and an aluminum bit line 13. The channel region 6 and the drain region 7 form a semiconductor pillar 3 on a portion of the source region 19.
To bring the semiconductor pillar 3 into contact with the bit line 13, a contact hole 13a as shown in FIGS. 1 and 2 in the interlaminar insulating film 12, by a photolithography process. In the process of forming the contact holes 13a, the positioning of the second conductive layer 7 and the contact hole 13a (in FIG. 1) and of the drain region 7 and the contact hole 13a (FIG. 2) is necessary at the exposure, and accordingly the whole head portion of the semiconductor pillar cannot be used for the contact, and thus the diameter of the semiconductor pillar must be enlarged.
FIGS. 3A to FIGS. 3G show cross-sectional step views of the production of another DRAM cell according to the prior art.
First, as shown in FIG. 3A, a SiO.sub.2 film 2 having a thickness of 0.5 .mu.m, an n.sup.+ conductive layer 4, a p.sup.- silicon layer 5 having a thickness of 5 .mu.m, a p channel doped layer 6, and a n.sup.+ conductive layer 7 are formed on a silicon substrate 1.
Then, as shown in FIGS. 3B(1) a trench 15 is formed by etching the semiconductor layers (7, 6, 5 and 4) by an RIE process using an oxide film 14 as a mask. Each semiconductor pillar 3 obtained by the etching has a top surface cross section of 0.7 .mu.m by 0.7 .mu.m and the gap d1 between pillars in the X-direction is greater than that (d2) in the Y-direction, as shown in the top plan view of FIG. 3B(2). Then, as shown in FIG. 3C, after removing the mask 14 a SiO.sub.2 film 17 and n.sup.+ poly Si film 18 are formed; thereafter, the exposed SiO.sub.2 film 17 is etched by hydrofluoric acid so that only the non-exposed portion of the dielectric SiO.sub.2 film 17 (i.e., the portion between the pillar 3 and the film 18) remains.
Then, as shown in FIG. 3D(1) the structure is thermally oxidized and a gate SiO.sub.2 film 17a having a thickness of 200 .ANG. is formed. Further, after forming a poly Si film by a CVD process on the exposed surface of the substrate, the poly Si film is etched back by an RIE process so that a side wall poly Si film 20, which becomes a gate electrode, remains; as explained above, different gaps are set up between the pillars, i.e., d1 is larger than d2 as shown in FIG. 3D(2).
Then, as shown in FIG. 3E, a SiO.sub.2 film 17b is formed by thermal oxidation and a layer 21 of phospho-silicate-glass (PSG) or SiO.sub.2 is deposited over the entire surface of the substrate by a CVD process.
Then, as shown in FIG. 3F, the deposited PSG or SiO.sub.2 layer 21 is etched back until the top surface of the semiconductor pillar is exposed.
Then an aluminum film is deposited and patterned so that a bit line 22 is formed, and the bit line 22 and the n.sup.+ conductive layer 7 in the semiconductor pillar are connected by a self alignment process. The above description is of a DRAM realized by a prior art, and in the etching back process shown in FIG. 3F the end point of the etching, wherein the semiconductor pillar is exposed, is not easily found, and therefore, since overetching in often carried out, the SiO.sub.2 film 17 at the upper corner position A in FIG. 3F is also etched, whereby the desired thickness of the SiO.sub.2 film can not be maintained and the breakdown voltage is lowered.